发信人: siemens()
整理人: camelsu(2001-01-30 01:24:14), 站内信件
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愿意合买的EMAIL TO ME
----19990808pm4:22 thw
I抎 like to see more people experimenting/playing with small CPU desig
ns, extending our knowledge of what
is possible with 憁inimal?nbsp;amounts of hardware and software. Toward th
at end, I propose to lead an
exploration of two CPUs, my QS5 Baby-RISC and a 16-bit implementation
of Chuck Moore抯 dual-stack
architecture. Both of these CPUs can be implemented in a small, low-co
st, FPGA connected to a PC抯
parallel port. Of course, the software running on them will be Forth.
We can meet monthly during the SVFIG
morning session for as long as you are interested, with lots of work a
nd electronic communication in between.
The designs for the two CPUs are in the HDL (hardware design language)
Verilog, and the Xilinx design
software will translate this to gates without having to write schemati
cs (logic synthesis). I strongly recommend
the book HDL Chip Design as a Rosetta stone, as it shows the Verilog a
nd VHDL (the other major HDL)
code for many common components along with the synthesized logic.
The tools for the chip's soft
ware are in Forth, and will run under either Win32Forth or SwiftForth.
The QS5
has a target assembler, dissa
sembler, metacompiler, and a few tools, plus the Forth source of e4th.
I抦 not
sure what tools Dr. Ting has
for the P16, but in the best Forth tradition, we抣l develop what we ne
ed as we go.
Prentice-Hall has published a
Xilinx FPGA lab book and win95/NT software which includes a coupon fo
r an
XESS FPGA board. Adding the c
ost of a power supply, you can be doing experiments for less than $250
.
The MAJOR drawback to the Xil
inx software is that it wants 350MB of your hard disk to install, alth
ough it
ONLY leaves 150MB there! MAJO
R BLOATWARE! Other limitations are the lack of human support from
Xilinx (they get no royalties
from Prentice Hall!) and the limited number of installs you can do (i
t抯 a
node-locked license with auto
matic registration through their web page, limited to 3 different driv
e IDs-don't
reformat your drive).
Getting started
Before the May 22nd first class meeting: purchase, install, and get fa
miliar with the Xilinx software and XESS board (by working through som
e of the lab examples)
and install one of the Forth systems. Send me an email when you're rea
dy to go, and I'll add you to a class email list so that we can do thi
s collaboratively.
Jeff Fox has offered to provide a live connection for people who can't
make it to the Silicon Valley FIG meetings. He's planning on videotap
ing the presentations,
displaying occasional snapshots in one frame, while running a chat-roo
m connection in another.
Required materials
Xilinx Student Edition 1.5, 1999, Prentice-Hall, ISBN 0-13-020586-9 (
Computer Literacy, $87+tax).
XESS XS40-005XL Board, $109 includes shipping, or $169 for the XS40-01
0XL, from XESS using the coupon in Xilinx Student Edition 1.5.
Win32Forth, free on the FIG page or SwiftForth, about $400 from Forth,
Inc.
These all run on a PC under Windows 95 or NT, and want 64MB of RAM (ne
ed 32MB) and LOTS of disk space.
Highly Recommended
HDL Chip Design, Douglas J. Smith, 1998, Doone Publications, ISBN 0-96
51934-3-8 ( Computer Literacy, $65+tax).
A Verilog simulator that can handle the 1200 lines of code in the cpu
and test fixture files. There are some demo/low-cost(?) ones listed he
re. (The Xilinx package
only supports functional, not behavioral/rtl, simulation, which makes
testing the cpu too tedious to consider.)
--
----提升你的电子设计水平的理想选择-----
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http://www.zhangjiang.gd.cn/personal/thw
http://siemens.163.net
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