发信人: siemens()
整理人: camelsu(2001-01-30 01:30:09), 站内信件
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---from free-ip.com
The Free-RAM core is a simple, portable, and parameterized RAM useful
for many applications. It's key features are:
Portable -- A portable RAM core is essential for writing VHDL code th
at can work on many types of FPGA's and ASIC's. It has been ported to
Xilinx Foundation, Altera Quartus, and ModelTech ModelSIM platforms.
Other platforms will be added.
Parameterized -- The same entity can be used for any size of RAM.
Automatically uses the most appropriate RAM for the target device (I.
E., in a Xilinx Virtex it will automatically switch between LUT based
RAM's and Block Select RAM's).
100% VHDL design makes code management much easier (I.E., version con
trol software, archiving, etc).
Currently, this core only contains a simple dual port RAM (one read po
rt, one write port). This is the most used type of RAM in FPGA's and
also happens to be the most common denominator among them. In the fut
ure, other types of RAM will be supported, although this type is the m
ost portable and the most immediately useful type of RAM.
Device Dependant Notes
Xilinx Foundation
Currently, if a RAM block is less than 2 kbits it will be implemented
with LUT's. RAM's of 2 kbits and larger will be made using the Block
Select RAM of the Virtex series of FPGA's. This can be overwritten us
ing the block_type flag.
Since the Virtex Block Select RAM only has synchronous read ports, all
async-read port RAM's will be made using LUT's.
This core works with chips other than the Virtex, although care should
be taken when making RAM's of larger than 2 kbits.
There is a bug in the Xilinx Foundation simulator. The RAM may fail t
o simulate properly if using the functional simulation mode. It appea
rs to work properly when using the timing simulator.
Altera Quartus
This library creates RAM using the embedded system blocks.
Since Quartus only supports the APEX line of parts, this library has o
nly been tested in those.
There is a bug in the Altera Quartus simulator. It appears that with
some RAM configurations using the functional simulation mode the test
bench will fail. This doesn't happen when using the timing simulation
mode.
Quartus must be set to use the VHDL-1993 specification. Do this by se
lecting Project/General_Settings from the menu and clicking on the VHD
L Input tab. From there, select VHDL 1993.
Model TECH ModelSIM
See the Free-IP FAQ regarding special ModelSIM settings.
Other Platforms
While the Free-RAM core hasn't been tested on other platforms, there a
re a couple that it might work fine on. Specifically:
Altera MAX II+ might work with the Free-RAM core (Quartus version).
Synplify, from Synplicity, might work with the ModelSIM version of the
RAM core.
Tips & Tricks
Writing portable VHDL code that takes full advantage of the target arc
hitecture is difficult and often filled with compromises-- and RAM is
no different. Here are some tips and tricks that will help you use th
e Free-RAM core effectively.
Use synchronous reads, especially on larger (>1kbit) RAM's. This hel
ps with timing issues and makes it possible to use the Xilinx Virtex B
lock Select RAM's.
Don't read and write to the same location at the same time. This may
result in undesired effects. At the very least the read could give b
ad data, but depending on the target device it could result in a bad w
rite.
Optimize the RAM size for the expected device, but keep in mind other
devices as well. The Altera Apex 20K devices has 2kbit RAM blocks, w
hile the Xilinx Virtex has 4k bit blocks. But also remember that Alte
ra Apex devices don't have any small RAM blocks (a.la, Xilinx LUT's).
--
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